1. Field of Invention
The present invention relates to a digital-to-analog converter. More particularly, the present invention relates to a digital-to-analog converter which can greatly reduce the layout area of analog voltage lines.
2. Description of Related Art
The apparatus for driving a display panel, e.g. an liquid crystal display (LCD) panel, is used for controlling and driving display panel according to the digital input data output by a timing controller. FIG. 1 is a block diagram illustrating a conventional N-channel, (M+L)-bit driving apparatus. Referring to FIG. 1, a shift register 101, a first line latch 102, a second line latch 103, a level shifter 104, an (M+L)-bit digital-to-analog converter (DAC) 105, a reference voltage source 107, and an N-channel output buffer 106 are included.
The clock signal CLK and the first control signal CT1 are used for activating the shift register 101, and the second control signal CT2 is used for controlling the second line latch 103. When the first control signal CT1 goes to a high level, the shift register 101 gradually shifts the received first control signal CT1 based on the clock signal CLK to output (N/3) latch signals of different phases to the first line latch 102. The first line latch 102 receives and latches the (M+L)-bit red, green, and blue (RGB) digital input data streams Din1, Din2, and Din3 based on the latch signals output by the shift register 101. When the digital input data streams of the entire line have been latched to the first line latch 102, the second control signal CT2 goes to a high level, accordingly, the data latched in the first line latch 102 is transmitted and latched to the second line latch 103. The level shifter 104 converts the digital data latched in the second line latch 103 into data of higher voltage level so as to accurately drive the digital-to-analog conversion unit 105. The digital-to-analog conversion unit 105 produces the corresponding analog output data based on the digital latch data output by the level shifter 104 and the analog voltage provided by the reference voltage source 107. The output buffer 106 is used for enhancing the driving capability to the output load and bringing the output to an expected analog voltage level. Then, the clock signal CLK and the first control signal CT1 become high level again, the data in the first line latch 102 is updated and latched. The above operations will be executed repeatedly.
FIG. 2 is a block diagram illustrating a conventional (M+L)-bit digital-to-analog conversion unit 105. Referring to FIG. 2, the digital-to-analog conversion unit 105 includes DACs 201-1, 201-2 . . . 201-N. The reference voltage source 107 provides 2M+L analog voltages Y(1), Y(2) . . . Y(2M+L) of different levels to the digital-to-analog conversion unit 105 through 2M+L analog voltage lines. The 2M+L analog voltage lines pass through the digital-to-analog conversion unit 105 to transmit the 2M+L analog voltages Y(1) to Y(2M+L) of different levels to each of the DACs 201-1 to 201-N. Each of the DACs 201-1 to 201-N respectively selects one of the analog voltages Y(1) to Y(2M+L) provided by the reference voltage source 107 based on the corresponding digital data output by the level shifter 104, and transmits the selected voltage level to the display panel through the output buffer 106.
The disadvantage of the conventional display panel driving apparatuses shown in FIGS. 1 and 2 is that the analog voltage lines in the digital-to-analog conversion unit 105 take a lot of chip area, in particular, the higher the resolution, the larger the area taken by the analog voltage lines. For example, if (M+L) is 8-bit, then 28 (i.e. 256) analog voltage lines are required in the digital-to-analog conversion unit 105. If (M+L) is 10-bit (to increase the resolution), then 210 (i.e. 1024) analog voltage lines are required in the digital-to-analog conversion unit 105. Accordingly, the chip area thereof will be very large and the manufacturing cost of the apparatus for driving display panel will be increased considerably.